1. Field of Use
The present invention relates to digital counters. More particularly, the present invention relates to digital counters having a glitchless terminal count indication for use with high speed control or sequencing systems.
2. Background Art
Many different types of digital counters having numerous desirable features are known in the art. For example, bidirectional synchronous binary or decade counters with preset capabilities for programmable operation and lookahead carry capabilities are available as integrated circuits under Signetics product numbers 74F168, 74F169, 74F568, and 74F569. The latter two products provide additional features such as a master reset which overrides all other inputs, a synchronous reset which overrides counting and parallel loading, and a clocked carry output which can be used as a clock for flip-flops, registers, and counters. While such counters and other counters of the art have many desirable features, they are prone to occasional glitches at the terminal count signal output due to unequal delays of the output lines, as may be seen with reference to the prior art counter of FIG. 1.
As shown in FIG. 1, a four bit counter 10 comprises a next state decode 15, state flip-flops 20, a terminal count decode 25 and a terminal count enable circuit 35. The next state decode has a our bit preset input (D0...D3) as well as up/down direction (U/D'), count enable trickle (CET'), count enable parallel (CEP'), and parallel enable (PE') active low control inputs. The four bit output of the next state decode 15 is coupled to the input of the state flip-flops 20 and provides the state flip-flops with the code representing the state that the state flip-flops will assume at the next clock cycle. The state flip-flops 20 which receive the clock signal (CLK) provides at its output an output count (Q0...Q3) which is also used as feedback to the next state decode 15. The output of the state flip-flops 20 is further provided to the terminal count decode 25 which causes, upon the recognition of a terminal count, the terminal count enable circuit 35 to provide a terminal count signal upon reaching the terminal count. Because each of the four bits of the output of the state flip-flops can experience different delays, glitches in the terminal count signal TC' (e.g. "1111" for a four-bit up count, and "0000" for a four bit down count) can occur. For example, when the state flip-flops are changing from a digital output of "0111" to "1000", if the most significant bit changes before the any of the other bits change, a terminal count signal "1111" may be seen by the terminal count decode 25. Despite the fact that the duration of the terminal count signal would be brief, a glitch at the output might occur. Similar incorrect terminal count signals, depending on the speeds of the state flip-flop output lines are possible at the digital transition from "1011" to "1101" and "1101" to "1110".
In order to eliminate terminal count glitches such as might occur in the circuitry of FIG. 1, many counters such as the above-referenced 74F568 and 74F569 counters have utilized a gated carry output. While terminal count output glitches are eliminated by the gated carry output, the advantageous results come at the cost of additional circuitry and a terminal count indication which extends only for a partial width of the clock pulse. Circuits such as disclosed in Japanese Kokai No. 53-142161 which replace the gated carry with a flip-flop, still only provide a terminal count which extends for at most one half a clock period. Moreover, such a circuit tends to be slower, which is disadvantageous in an environment demanding increasingly faster circuits.
Finally, a glitchless counter using different principles is disclosed by T.M. Farr, Jr., in EDN, 19, nr.18, Sept. 20, 1974 (p.78). The provided counter is implemented with first and second levels having a plurality of T-type flip-flops, where the "Q" output of each stage of the first level is connected to the "T" (toggle) input of the corresponding stage of the second level. The resulting glitchless counter, however, has various drawbacks such as the output being a Gray code output, and the circuitry requiring approximately twice as many flip-flops as are required in the typical counters of the art. Moreover, the provided counter is designed to remove glitches on the Q outputs of the flip-flops rather than on the total count output indicator.